BUF0I=BUF0I_0, BUF7I=BUF7I_0, BUF5I=BUF5I_0, BUF6I=BUF6I_0
Interrupt Flags 1 register
| BUF0I | Buffer MB0 Interrupt Or Clear Legacy FIFO bit 0 (BUF0I_0): The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0. 1 (BUF0I_1): The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0. |
| BUF4TO1I | Buffer MB i Interrupt Or “reserved” |
| BUF5I | Buffer MB5 Interrupt Or “Frames available in Legacy Rx FIFO” 0 (BUF5I_0): No occurrence of MB5 completing transmission/reception when CAN_MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when CAN_MCR[RFEN]=1 1 (BUF5I_1): MB5 completed transmission/reception when CAN_MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when CAN_MCR[RFEN]=1. It generates a DMA request in case of CAN_MCR[RFEN] and CAN_MCR[DMA] are enabled. |
| BUF6I | Buffer MB6 Interrupt Or “Legacy Rx FIFO Warning” 0 (BUF6I_0): No occurrence of MB6 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 1 (BUF6I_1): MB6 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 |
| BUF7I | Buffer MB7 Interrupt Or “Legacy Rx FIFO Overflow” 0 (BUF7I_0): No occurrence of MB7 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 1 (BUF7I_1): MB7 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 |
| BUF31TO8I | Buffer MBi Interrupt |